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5 chipset chipset chipset chipset chipset – Asus P5GPL User Manual

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C h a p t e r 4 : B I O S s e t u p

C h a p t e r 4 : B I O S s e t u p

C h a p t e r 4 : B I O S s e t u p

C h a p t e r 4 : B I O S s e t u p

C h a p t e r 4 : B I O S s e t u p

2.4.5

2.4.5

2.4.5

2.4.5

2.4.5

Chipset

Chipset

Chipset

Chipset

Chipset

The Chipset menu allows you to change the advanced chipset settings.
Select an item then press to display the sub-menu.

Select Screen
Select Item
+

Ch

O ti

Execute Disable Function [Auto]

Execute Disable Function [Auto]

Execute Disable Function [Auto]

Execute Disable Function [Auto]

Execute Disable Function [Auto]

Enables or disables the Execute Disable function.
Configuration options: [Disabled] [Enabled]

Enhanced C1 Control [Auto]

Enhanced C1 Control [Auto]

Enhanced C1 Control [Auto]

Enhanced C1 Control [Auto]

Enhanced C1 Control [Auto]

When set to [Auto], the BIOS will automatically check the CPU’s capability
to enable the C1E support. In C1E mode, the CPU power consumption is
lower when idle. Configuration options: [Auto] [Disabled]

CPU Internal Thermal Control [Auto]

CPU Internal Thermal Control [Auto]

CPU Internal Thermal Control [Auto]

CPU Internal Thermal Control [Auto]

CPU Internal Thermal Control [Auto]

Disables or sets the CPU internal thermal control.
Configuration options: [Disabled] [Auto]

Hyper-Threading Technology [Enabled]

Hyper-Threading Technology [Enabled]

Hyper-Threading Technology [Enabled]

Hyper-Threading Technology [Enabled]

Hyper-Threading Technology [Enabled]

Allows you to enable or disable the processor Hyper-Threading Technology.
Configuration options: [Disabled] [Enabled]

Advanced Chipset Settings

Configure DRAM Timing by SPD

[Enabled]

Hyper Path 2

[Auto]

Graphic Adapter Priority

[PCI Express/PCI]

PEG Buffer Length

[Auto]

Link Latency

[Auto]

PEG Link Mode

[Auto]

PEG Root Control

[Auto]

Slot Power

[Auto]

Advanced Chipset Settings

Advanced Chipset Settings

Advanced Chipset Settings

Advanced Chipset Settings

Advanced Chipset Settings

Configure DRAM Timing by SPD [Enabled]

Configure DRAM Timing by SPD [Enabled]

Configure DRAM Timing by SPD [Enabled]

Configure DRAM Timing by SPD [Enabled]

Configure DRAM Timing by SPD [Enabled]

When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters through the DRAM sub-items.
The following sub-items appear when this item is Disabled.
Configuration options: [Disabled] [Enabled]

DRAM CAS# Latency [3 Clocks]
Controls the latency between the SDRAM read command and the time
the data actually becomes available.
Configuration options: [3 Clocks] [2.5 Clocks] [2 Clocks]