2 core specifications – Asus P4B533 User Manual

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1-8

Chapter 1: Product introduction

ASUS EZ Plug™ +12V connector. This ASUS patented auxilliary
power connector is used if you don’t have an ATX +12V power
supply. Connect a 4-pin device connector from a standard power
supply to this connector to provide sufficient power to the CPU.

ATX 12V connector. This power connector connects the 4-pin 12V
plug from the ATX 12V power supply.

DIP switches (DSW1). This 6-switch Dual Inline Package (DIP)
allows you to set the CPU external frequency.

CPU socket. A 478-pin surface mount, Zero Insertion Force (ZIF)
socket for the Intel

Pentium

4 Processor, with 533/400 MHz

system bus that allows 4.3GB/s and 3.2GB/s data transfer rates,
respectively.

North bridge controller. The Intel

845E Memory Controller Hub

(MCH) provides the processor interface with 533/400MHz
frequency, system memory interface at 133/100MHz operation, and
1.5V AGP interface that supports AGP 2.0 specification including
2X/4X Fast Write protocol. The MCH interconnects to the south
bridge ICH4 via the Intel proprietary Hub Interface.

DDR DIMM sockets. These three 184-pin DIMM sockets support
up to 2GB system memory using unbuffered ECC or non-ECC
PC2100/1600 DDR DIMMs.

Floppy disk connector. This connector accommodates the
provided ribbon cable for the floppy disk drive. One side of the
connector is slotted to prevent incorrect insertion of the floppy disk
cable.

ATX power connector. This 20-pin connector connects to an ATX
+12V power supply. The power supply must have at least 1A on the
+5V standby lead (+5VSB).

South bridge controller. The fourth-generation Intel I/O Controller
Hub (ICH4) is a subsystem that integrates various I/O functions
including 2-channel ATA/100 bus master IDE controller, up to six
USB 2.0/1.1 ports, I/O APIC, SMBus 2.0 controller, LPC interface,
AC’97 2.2 interface, PCI 2.2 interface, and integrated LAN
controller. The ICH4 also contains the necessary arbitration and
buffering for efficient utilization of these interfaces.

1.4.2 Core specifications