Rainbow Electronics MAX545 - Manual (Page 3)

MAX544/MAX545
+5V, Serial-Input, Voltage-Output, 14-Bit DACs
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ELECTRICAL CHARACTERISTICS (continued)
(V DD = +5V ± 5%, V REF = +2.5V, AGND = DGND = 0, T A = T MIN to T MAX , unless otherwise noted.)
TIMING CHARACTERISTICS
(V DD = +5V ± 5%, V REF = +2.5V, AGND = DGND = 0, CMOS inputs, T A = T MIN to T MAX , unless otherwise noted.)
Note 1: Gain Error tested at V REF = 2.0V, 2.5V, and 3.0V.
Note 2: R OUT tolerance is typically ±20%.
Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code dependent, minimum at 8554 hex.
Note 5: Slew-rate value is measured from 0% to 63%.
Note 6: Guaranteed by design. Not production tested.
Code = FFFC hex
V IN = 0
Code = 0000 hex, V REF = 1Vp-p at 100kHz
Code = 0000 hex
Code = FFFC hex
(Note 6)
CONDITIONS
mW 1.5 PD Power Dissipation
mA 0.3 1.1 I DD Positive Supply Current
V 4.75 5.25 V
DD
Positive Supply Range
V 0.40 V H Hysteresis Voltage
pF 10 C IN Input Capacitance
mVp-p 1
MHz 1 BW Reference -3dB Bandwidth
µA ±1 I IN Input Current
V 0.8 V IL Input Low Voltage
V 2.4 V IH Input High Voltage
Reference Feedthrough
dB 83 SNR Signal-to-Noise Ratio
75
pF
120
C IN Reference Input Capacitance
UNITS MIN TYP MAX SYMBOL PARAMETER
MAX545 (Note 6)
MAX545
(Note 6)
CONDITIONS
µs 20
V DD High to CS Low
(power-up delay)
ns 45 t CL SCLK Pulse Width Low
ns 45 t CH
MHz 10 f SCLK SCLK Frequency
SCLK Pulse Width High
ns 50 t LDACS
CS High to LDAC Low Setup
ns 50 t LDAC LDAC Pulse Width
ns 0 t DH DIN to SCLK High Hold
ns 40 t DS DIN to SCLK High Setup
ns 45 t CSS0
CS Low to SCLK High Setup
ns 45 t CSS1
CS High to SCLK High Setup
ns 30 t CSH0 SCLK High to CS Low Hold
ns 45 t CSH1 SCLK High to CS High Hold
UNITS MIN TYP MAX SYMBOL PARAMETER
DYNAMIC PERFORMANCE—REFERENCE SECTION
STATIC PERFORMANCE—DIGITAL INPUTS
POWER SUPPLY