Rainbow Electronics MAX1195 - Manual (Page 5)

MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
CLK
0.8 ×
V DD
Input High Threshold V IH
PD, OE, SLEEP, T/B
0.8 ×
OV DD
V
CLK
0.2 ×
V DD
Input Low Threshold V IL
PD, OE, SLEEP, T/B
0.2 ×
OV DD
V
Input Hysteresis V HYST 0.15 V
I IH V IH = V DD = OV DD
±20
Input Leakage
I IL V IL = 0 ±20
µA
Input Capacitance C IN 5 pF
DIGITAL OUTPUTS ( D7A–D0A, D7B–D0B)
Output Voltage Low V OL I SINK = -200µA 0.2 V
Output Voltage High V OH I SOURCE = 200µA
OV DD
- 0.2
V
Three-State Leakage Current I LEAK
OE = OV
DD
±10 µA
Three-State Output Capacitance C OUT
OE = OV
DD 5 pF
POWER REQUIREMENTS
Analog Supply Voltage Range V DD 2.7 3 3.6 V
Output Supply Voltage Range OV DD C L = 15pF 1.7 3 3.6 V
Operating, f INA & B = 20MHz at
-1dB FS applied to both channels
29 36
Sleep mode 3
mA
Analog Supply Current I VDD
Shutdown, clock idle, PD = OE = OV
DD 0.1 20 µA
Operating, f INA & B = 20MHz at
-1dB FS applied to both channels (Note 6)
8 mA
Sleep mode 3
Output Supply Current I OVDD
Shutdown, clock idle, PD = OE = OV
DD 3 10
µA
Operating, f INA & B = 20MHz at
-1dB FS applied to both channels
87 108
Sleep mode 9
mW
Analog Power Dissipation PDISS
Shutdown, clock idle, PD = OE = OV
DD 0.3 60 µW
Offset, V DD
±5% ±3
Power-Supply
Rejection
PSRR
Gain, V DD
±5% ±3
mV/V
ELECTRICAL CHARACTERISTICS (continued)
(V DD = OV DD = 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k Ω
resistor, V IN = 2V P-P (differential with respect to COM), C L = 10pF at digital outputs, f CLK = 40MHz, T A = T MIN to T MAX , unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at
T A = +25°C.)