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Table 2. detailed sspstat register content – Rainbow Electronics MAX1289 User Manual

Page 12

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MAX1286–MAX1289

Layout, Grounding, and Bypassing

For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only

one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.

High-frequency noise in the power supply (V

DD

) may

degrade the performance of the ADC’s fast comparator.
Bypass V

DD

to the star ground with a 0.1µF capacitor,

located as close as possible to the MAX1286–MAX1289s’
power-supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5

) if

the power supply is extremely noisy.

150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23

12

______________________________________________________________________________________

CNVST

SCLK

DOUT

CS

SCK

MISO

V

DD

SS

QSPI

MAX1286–
MAX1289

Figure 9a. QSPI Connections

Table 2. Detailed SSPSTAT Register Content

CONTROL BIT

MAX1286–MAX1289

SETTINGS

SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)

SMP

Bit 7

0

SPI Data Input Sample Phase. Input data is sampled at the middle of the data
output time.

CKE

Bit 6

1

SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial
clock.

D/A

Bit 5

X

Data Address Bit

P

Bit 4

X

Stop Bit

S

Bit 3

X

Start Bit

R/W

Bit 2

X

Read/Write Bit Information

UA

Bit 1

X

Update Address

BF

Bit 0

X

Buffer Full Status Bit

Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)

CNVST

1ST BYTE READ

SCLK

DOUT

2ND BYTE READ

SAMPLING INSTANT

4

1

8

12

B11

MSB

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

LSB

HIGH-Z

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