Rainbow Electronics DS1846 - Manual (Page 5)

DS1846
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Write Operations: After receiving a matching device address byte with the R/W bit set low, the device
goes into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to
the device to define the address where the data is to be written. After the reception of this byte, the
DS1846 will transmit a zero for one clock cycle to acknowledge the receipt of the memory address. The
master must then transmit an 8-bit data word to be written into this memory address. The DS1846 will
again transmit a zero for one clock cycle to acknowledge the receipt of the data byte. At this point the
master must terminate the write operation with a stop condition. The DS1846 then enters an internally
timed write process T
w
to the EEPROM memory. All inputs other than those controlling the
MicroMonitor are disabled during this write cycle.
The DS1846 is capable of an 8-byte page write. A page write is initiated the same way as a byte write,
but the master does not send a stop condition after the first data byte. Instead, after the slave
acknowledges receipt of the data byte, the master can send up to seven more data bytes using the same
nine-clock sequence. After a write to the last byte in the page, the address returns to the beginning of the
page. The master must terminate the write cycle with a stop condition or the data clocked into the
DS1846 will not be latched into permanent memory.
Acknowledge Polling: Once the internally-timed write has started and the DS1846 inputs are disabled,
acknowledge polling can be initiated. The process involves transmitting a start condition followed by the
device address. The R/W bit signifies the type of operation that is desired. The read or write sequence
will only be allowed to proceed if the internal write cycle has completed and the DS1846 responds with a
zero.
Read Operations: After receiving a matching address byte with the R/W bit set high, the device goes
into the read mode of operation. There are three read operations: current address read, random read and
sequential address read.
CURRENT ADDRESS READ
The DS1846 has an internal address register that maintains the address used during the last read or write
operation, incremented by one. This data is maintained as long as V
CC
is valid. If the most recent
address was the last byte in memory, then the register resets to the first address. This address stays valid
between operations as long as power is available.
Once the device address is clocked in and acknowledged by the DS1846 with the R/W bit set to high, the
current address data word is clocked out. The master does not respond with a zero, but does generate a
stop condition afterwards.
RANDOM READ
A random read requires a dummy byte write sequence to load in the data word address. Once the device
address and data bytes are clocked in by the master, and acknowledged by the DS1846, the master must
generate another start condition. The master now initiates a current address read by sending the device
address with the read/write bit set high. The DS1846 will acknowledge the device address and serially
clocks out the data byte.
SEQUENTIAL ADDRESS READ
Sequential reads are initiated by either a current address read or a random address read. After the master
receives the first data byte, the master responds with an acknowledge. As long as the DS1846 receives
this acknowledge after a byte is read, the master may clock out additional data words from the DS1846.
After reaching address FFh, it resets to address 00h.