Rainbow Electronics AT90LS2343 - Manual (Page 19)

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AT90S/LS2323/2343
1004D–09/01
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc-
tion Set description for detailed information.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
Stack Pointer – SPL A n 8 - b i t r e g i s t e r a t I / O a d d re s s $ 3 D ( $ 5 D ) f o r m s t h e s t a c k p o i n t e r o f t h e
AT90S2323/2343. Eight bits are used to address the 128 bytes of SRAM in locations
$60 - $DF.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter-
rupt stacks are located. This stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when
data is pushed onto the Stack with the PUSH instruction and it is decremented by 2
when an address is pushed onto the stack with subroutine calls and interrupts. The
Stack Pointer is incremented by 1 when data is popped from the stack with the POP
instruction and it is incremented by 2 when an address is popped from the stack with
return from subroutine RET or return from interrupt RETI.
Reset and Interrupt
Handling The AT90S2323/2343 provides two interrupt sources. These interrupts and the separate
reset vector each have a separate program vector in the program memory space. Both
interrupts are assigned individual enable bits that must be set (one) together with the
I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 3. The list
also determines the priority levels of the interrupts. The lower the address, the higher
the priority level. RESET has the highest priority, and next is INT0 (the External Interrupt
Request 0), etc.
Bit 7 6 5 4 3 2 1 0
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 3. Reset and Interrupt Vectors
Vector No. Program Address Source Interrupt Definition
1 $000 RESET
Hardware Pin, Power-on Reset and
Watchdog Reset
2 $001 INT0 External Interrupt Request 0
3 $002 TIMER0, OVF0 Timer/Counter0 Overflow