Ac electrical characteristics, Applications information – Rainbow Electronics DS92LV090A User Manual
Page 5
AC Electrical Characteristics
(Continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t
PHZ
Disable Time High to Z
R
L
= 500
Ω
,
Figures 8, 9,
C
L
= 35 pF
4.5
10
ns
t
PLZ
Disable Time Low to Z
3.5
8
ns
t
PZH
Enable Time Z to High
3.5
8
ns
t
PZL
Enable Time Z to Low
3.5
8
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except
V
OD
,
∆
V
OD
and V
ID
.
Note 3: All typicals are given for V
CC
= +3.3V and T
A
= +25˚C, unless otherwise stated.
Note 4: ESD Rating: HBM (1.5 k
Ω
, 100 pF)
>
4.5 kV EIAJ (0
Ω
, 200 pF)
>
300V.
Note 5: C
L
includes probe and fixture capacitance.
Note 6: Generator waveforms for all tests unless otherwise specified: f = 25 MHz, Z
O
= 50
Ω
, t
r
, t
f
=
<
1.0 ns (0%–100%). To ensure fastest propagation delay and
minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate,
the better the AC performance.
Note 7: The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs.
Note 8: Propagation delays are guaranteed by design and characterization.
Note 9: t
SKD1
|t
PHLD
–t
PLHD
| is the worse case skew between any channel and any device over recommended operation conditions.
Note 10: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.
Note 11: V
OH
failsafe terminated test performed with 27
Ω
connected between RI+ and RI− inputs. No external voltage is applied.
Note 12: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
Note 13: Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, either edge.
Applications Information
General application guidelines and hints may be found in the
following application notes: AN-808, AN-903, AN-971,
AN-977, and AN-1108.
There are a few common practices which should be implied
when designing PCB for Bus LVDS signaling. Recom-
mended practices are:
•
Use at least 4 PCB board layer (Bus LVDS signals,
ground, power and TTL signals).
•
Keep drivers and receivers as close to the (Bus LVDS
port side) connector as possible.
•
Bypass each Bus LVDS device and also use distributed
bulk capacitance between power planes. Surface mount
capacitors placed close to power and ground pins work
best. Two or three high frequency, multi-layer ceramic
(MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in
parallel should be used between each V
CC
and ground.
The capacitors should be as close as possible to the V
CC
pin.
Multiple vias should be used to connect V
CC
and Ground
planes to the pads of the by-pass capacitors.
In addition, randomly distributed by-pass capacitors
should be used.
•
Use the termination resistor which best matches the dif-
ferential impedance of your transmission line.
•
Leave unused Bus LVDS receiver inputs open (floating).
Limit traces on unused inputs to
<
0.5 inches.
•
Isolate TTL signals from Bus LVDS signals
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
•
Use controlled impedance media. The backplane and
connectors should have a matched differential imped-
ance.
TABLE 1. Functional Table
MODE SELECTED
DE
RE
DRIVER MODE
H
H
RECEIVER MODE
L
L
TRI-STATE MODE
L
H
LOOP BACK MODE
H
L
TABLE 2. Transmitter Mode
INPUTS
OUTPUTS
DE
D
IN
DO+
DO−
H
L
L
H
H
H
H
L
H
0.8V
<
D
IN
<
2.0V
X
X
L
X
Z
Z
TABLE 3. Receiver Mode
INPUTS
OUTPUT
RE
(RI+) – (RI−)
L
L (
<
−100 mV)
L
L
H (
>
+100 mV)
H
L
−100 mV
<
V
ID
<
+100 mV
X
H
X
Z
X = High or Low logic state
L = Low state
Z = High impedance state
H = High state
DS92L
V090A
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