Rainbow Electronics DS1248Y - Manual (Page 11)

DS1248Y
032697 11/12
NOTES:
1. WE is high for a read cycle.
2. OE = V
IH
or V
IL
. If OE = V
IH
during write cycle, the output buffers remain in a high impedance state.
3. t
WP
is specified as the logical AND of CE and WE. t
WP
is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.
4. t
DH
, t
DS
are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 50 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
remain in a high impedance state during this period.
9. The expected t
DR
is defined as accumulative time in the absence of V
CC
with the clock oscillator running.
10. t
WR
is a function of the latter occurring edge of WE or CE.
11. t
DH
and t
DS
are a function of the first occurring edge of WE or CE.
12. RST (Pin1) has an internal pull–up resistor.
13. Real–Time Clock Modules can be successfully processed through conventional wave–soldering techniques as
long as temperature exposure to the lithium energy source contained within does not exceed +85
°
C. Post solder
cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.