Rainbow Electronics MAX8548 User Manual
Page 13
MAX8545/MAX8546/MAX8548
Low-Cost, Wide Input Range, Step-Down
Controllers with Foldback Current Limit
______________________________________________________________________________________
13
has a gain drop of 40dB per decade, and a phase shift
of 180°. The error amplifier must compensate for this
gain drop and phase shift to achieve a stable high-
bandwidth, closed-loop system.
The basic regulator loop consists of a power modulator
(Figure 3), an output feedback divider, and an error
amplifier. The power modulator has DC gain set by
V
IN
/V
RAMP
, with a double pole set by the inductor and
output capacitor, and a single zero set by the output
capacitor (C
OUT
) and its equivalent series resistance
(ESR). Below are equations that define the power mod-
ulator:
The DC gain of the power modulator is:
where V
RAMP
= 1V.
The pole frequency due to the inductor and output
capacitor is:
The zero frequency due to the output capacitor’s ESR is:
The output capacitor is usually comprised of several
same capacitors connected in parallel. With n capaci-
tors in parallel, the output capacitance is:
C
OUT
= n X C
EACH
The total ESR is:
The ESR zero (f
ZESR
) for a parallel combination of
capacitors is the same as for an individual capacitor.
The feedback divider has a gain of G
FB
= V
FB
/V
OUT
,
where V
FB
is 0.8V.
The transconductance error amplifier has DC gain
G
EA(dc)
of 72dB. A dominant pole (f
DPEA
) is set by the
compensation capacitor (C
C
), the amplifier output
resistance (R
O
) equals 37M
Ω, and the compensation
resistor (R
C
):
The compensation resistor and the compensation
capacitor set a zero:
The total closed-loop gain must equal unity at the
crossover frequency. The crossover frequency should
be higher than f
ZESR
, so that the -1 slope is used to
cross over at unity gain. Also, the crossover frequency
should be less than or equal to 1/5 the switching fre-
quency (f
SW
) of the controller.
The loop-gain equation at the crossover frequency is:
V
FB
/V
OUT
x G
EA(fC)
x G
MOD(fC)
= 1
where G
EA(fc)
= g
mEA
× R
C
, and G
MOD(fc)
= G
MOD(DC)
× (f
PMOD
)
2
/ (f
ZESR
× f
C
).
The compensation resistor, R
C
, is calculated from:
R
C
= V
OUT
/ g
mEA
x V
FB
x G
MOD(fC)
where g
mEA
= 108µS.
Due to the underdamped (Q > 1) nature of the output
LC double pole, the error-amplifier compensation zero
should be approximately 0.2 f
PMOD
to provide good
phase boost. C
C
is calculated from:
A small capacitor, C
F
, can also be added from COMP to
GND to provide high-frequency decoupling. C
F
adds
another high-frequency pole, f
PHF
, to the error-amplifier
response. This pole should be greater than 100 times the
error-amplifier zero frequency to have negligible impact
on the phase margin. This pole should also be less than
1/2 the switching frequency for effective decoupling.
100 f
ZEA
< f
PHF
< 0.5 f
sw
Select a value for f
PHF
in the range given above, then
solve for C
F
using the following equation:
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switch-
ing losses and stable operation. If possible, mount all the
power components on the top side of the board with their
C
R
f
F
C
PHF
=
Ч
Ч
1
2
π
C
R
f
C
C
PMOD
=
Ч
Ч
5
2
π
f
f
f
ZESR
C
SW
< ≤
5
f
C
R
ZEA
C
C
=
Ч
Ч
1
2
π
f
C
R
R
DPEA
C
O
C
=
Ч
Ч
+
(
)
1
2
π
ESR
ESR
n
EACH
=
f
ESR C
ZESR
OUT
=
Ч
Ч
1
2
π
f
LC
PMOD
OUT
=
1
2
π
G
V
V
MOD DC
IN
RAMP
(
)
=