Rainbow Electronics MAX8548 User Manual
Page 11
MAX8545/MAX8546/MAX8548
Low-Cost, Wide Input Range, Step-Down
Controllers with Foldback Current Limit
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11
A limitation of sensing current across a MOSFET’s on-
resistance is that the current-limit threshold is not accu-
rate since MOSFET R
DS(ON)
specifications are not
precise. This type of current limit provides a coarse level
of fault protection. It is especially suited when the input
source is already current-limited or otherwise protected.
Power MOSFET Selection
The MAX8545/MAX8546/MAX8548 drive two external,
logic-level, N-channel MOSFETs as the circuit switch-
ing elements. The key selection parameters are:
1) On-resistance (R
DS(ON)
): the lower, the better.
2) Maximum drain-to-source voltage (V
DSS
) should be
at least 10% higher than the input supply rail at the
high-side MOSFET’s drain.
3) Gate charges (Q
g
, Q
gd
, Q
gs
): the lower, the better.
Choose the MOSFETs with rated R
DS(ON)
at V
GS
= 4.5V
for an input voltage greater than 5V, and at V
GS
= 2.5V
for an input voltage less than 5.5V. For a good compro-
mise between efficiency and cost, choose the high-side
MOSFET (N1) that has conduction losses equal to the
switching losses at nominal input voltage and maximum
output current. For N2, make sure it does not spuriously
turn on due to a dV/dt caused by N1 turning on as this
would result in shoot-through current degrading the
efficiency. MOSFETs with a lower Q
gd
/ Q
gs
ratio have
higher immunity to dV/dt.
MOSFET Power Dissipation
For proper thermal-management design, the power dis-
sipation must be calculated at the desired maximum
operating junction temperature, maximum output cur-
rent, and worst-case input voltage (for the low-side
MOSFET (N2) the worst case is at V
IN(MAX)
, for the high-
side MOSFET (N1) the worst case can be either at
V
IN(MIN)
or V
IN(MAX)
). N1 and N2 have different loss
components due to the circuit operation. N2 operates as
a zero-voltage switch; therefore, the major losses are:
the channel conduction loss (P
N2CC
), the body-diode
conduction loss (P
N2DC
), and the gate-drive loss
(P
N2DR
).
Use R
DS(ON)
at T
J(MAX)
.
where V
F
is the body-diode forward voltage drop, t
dt
is
the dead time between N1 and N2 switching transitions
(which is 30ns), and f
S
is the switching frequency.
Because of zero-voltage switch operation, the N2 gate-
drive losses are due to charging and discharging the
input capacitor, C
ISS
. These losses are distributed
between the average DL gate driver’s pullup and pull-
down resistors and the internal gate resistance. The
R
DL
is typically 1.8
Ω, and the internal gate resistance
(R
GATE
) of the MOSFET is typically 2
Ω. The drive
power dissipated in N2 is given by:
N1 operates as a duty-cycle control switch and has the
following major losses: the channel conduction loss
(P
N1CC
), the voltage and current overlapping switching
loss (P
N1SW
), and the drive loss (P
N1DR
). N1 does not
have a body-diode conduction loss because the diode
never conducts current.
Use R
DS(ON)
at T
J(MAX)
.
where I
GATE
is the average DH high driver output-cur-
rent capability determined by:
where R
DH
is the high-side MOSFET driver’s average
on-resistance (2.05
Ω typ) and R
GATE
is the internal
gate resistance of the MOSFET (2
Ω typ).
where V
GS
~ VL.
In addition to the losses above, allow about 20% more
for additional losses due to MOSFET output capaci-
tance and N2 body-diode reverse recovery charge dis-
sipated in N1. Refer to the MOSFET data sheet for
thermal resistance specifications to calculate the PC
board area needed. This information is essential to
maintain the desired maximum operating junction tem-
perature with the above calculated power dissipation.
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side MOSFET drain to
the low-side MOSFET source or add resistors in series
P
Q
V
f
R
R
R
N DR
GS
GS
S
GATE
DH
GATE
1
=
Ч
Ч Ч
+
I
VL
R
R
GATE ON
DH
GATE
(
)
= ×
+
1
2
P
V
I
f
Q
Q
I
N SW
IN
LOAD
S
GS
GD
GATE
1
=
Ч
Ч Ч
+
P
V
V
I
R
N CC
OUT
IN
LOAD
DS ON
1
2
=
Ч
(
)
Ч
(
)
P
C
V
f
R
R
R
N DR
ISS
GS
S
GATE
GATE
DL
2
2
=
Ч
( )
Ч Ч
+
P
I
V
t
f
N DC
LOAD
F
dt
S
2
2
= Ч
Ч
Ч
Ч
P
V
V
I
R
N CC
OUT
IN
LOAD
DS ON
2
2
1
= −
Ч
Ч
(
)