Rainbow Electronics MAX5172 - Manual (Page 11)

MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
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The MAX5170/MAX5172 accepts one 16-bit packet or
two 8-bit packets sent while
CS remains low. The
MAX5170/MAX5172 allow the following to be config-
ured:
• Clock edge on which serial data output (DOUT) is
clocked out
• State of the user-programmable logic output
• Configuration of the reset state.
Specific commands for setting these are shown in
Table 1.
The general timing diagram in Figure 4 illustrates how
the MAX5170/MAX5172 acquire data.
CS must go low
at least t CSS before the rising edge of the serial clock
(SCLK). With CS low, data is clocked into the register
on the rising edge of SCLK. The maximum serial clock
frequency guaranteed for proper operation is 10MHz
for MAX5170 and 6MHz for MAX5172. See Figure 5 for
a detailed timing diagram of the serial interface.
Serial Data Output (DOUT)
The serial-data output, DOUT, is the internal shift regis-
ter’s output and allows for daisy-chaining of multiple
devices as well as data readback (see
Applications
Information). By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, the output data lags
DIN by 16.5 clock cycles and is clocked out on the ser-
ial clock’s rising edge. During shutdown, DOUT retains
its last digital state prior to shutdown.
Load input register; DAC registers are updated (start-up DAC with new data). 1 0
Load input register; DAC registers are unchanged. 0 0
14-bit DAC data
14-bit DAC data
16-BIT SERIAL WORD
D11..................D0 C1
FUNCTION
C0
No operation (NOP). 1 1 0 0 x xxx xxxx xxxx
x x x xxx xxxx xxxx
Update DAC register from input register (start-up DAC with data previously
stored in the input registers).
0 1
UPO goes low (default). 1 1 1 0 0 xxx xxxx xxxx
0 1 x xxx xxxx xxxx
Mode 1, DOUT clocked out on SCLK’s rising edge. 1 1 1 1 0 xxx xxxx xxxx
1 0 1 xxx xxxx xxxx UPO goes high. 1 1
Shut down DAC (provided PDL = 1). 1 1
Mode 0, DOUT clocked out on SCLK’s falling edge (default). 1 1 1 1 1 xxx xxxx xxxx
SCLK
DIN
CS
MOSI
SCK
+5V
I/O
CPOL = 0, CPHA = 0
SPI/QSPI
PORT
SS
MAX5170
MAX5172
Figure 2. Connections for SPI and QSPI Interface
SCLK
DIN
CS
SK
SO
I/O
MICROWIRE
PORT MAX5170
MAX5172
Figure 3. Connections for MICROWIRE Interface Standards
Table 1. Serial-Interface Programming Commands