Rainbow Electronics ADC0817 - Manual (Page 7)

Timing Diagram
(Continued)
The successive approximation register (SAR) performs 8 it-
erations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter.
Figure 2 shows a typical example of a 3-bit converter. In the
ADC0816, ADC0817, the approximation technique is ex-
tended to 8 bits using the 256R network.
The A/D converter’s successive approximation register
(SAR) is reset on the positive edge of the start conversion
(SC) pulse. The conversion is begun on the falling edge of
the start conversion pulse. A conversion in process will be in-
terrupted by receipt of a new start conversion pulse. Con-
tinuous conversion may be accomplished by tying the
end-of-conversion (EOC) output to the SC input. If used in
this mode, an external start conversion pulse should be ap-
plied after power up. End-of-conversion will go low between
0 and 8 clock pulses after the rising edge of start conversion.
The most important section of the A/D converter is the com-
parator. It is this section which is responsible for the ulimate
accuracy of the entire converter. It is also the comparator
drift which has the greatest influence on the repeatability of
the device. A chopper-stabilized comparator provides the
most effective method of satisfying all the converter require-
ments.
The chopper-stabilized comparator converts the DC input
signal into an AC signal. This signal is then fed through a
high gain AC amplifier and has the DC level restored. This
technique limits the drift component of the amplifier since the
drift is a DC component which is not passed by the AC am-
plifier. This makes the entire A/D converter extremely insen-
sitive to temperature, long term drift and input offset errors.
Figure 4 shows a typical error curve for the ADC0816 as
measured using the procedures outlined in AN-179.
Connection Diagram
DS005277-6
Order Number ADC0816CCN, ADC0817CCN,
ADC0816CCJ or ADC0816CJ
See NS Package Number J40A or N40A
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