Rainbow Electronics MAX15026 - Manual (Page 18)

MAX15026
Boost Capacitor
The MAX15026 uses a bootstrap circuit to generate the
necessary gate-to-source voltage to turn on the high-
side MOSFET. The selected n-channel high-side
MOSFET determines the appropriate boost capaci-
tance value (C
BST in the Typical Application Circuits )
according to the following equation:
where Q G is the total gate charge of the high-side
MOSFET and
∆V
BST is the voltage variation allowed on
the high-side MOSFET driver after turn-on. Choose
∆V
BST so the available gate-drive voltage is not signifi-
cantly degraded (e.g.
∆V
BST = 100mV to 300mV) when
determining C BST . Use a low-ESR ceramic capacitor as
the boost flying capacitor with a minimum value of
100nF.
Power Dissipation
The maximum power dissipation of the device depends
on the thermal resistance from the die to the ambient
environment and the ambient temperature. The thermal
resistance depends on the device package, PCB cop-
per area, other thermal mass, and airflow.
The power dissipated into the package (P T ) depends
on the supply configuration (see the Typical Application
Circuits ). Use the following equation to calculate power
dissipation:
P T = (V IN - V CC ) x I LDO + V DRV x I DRV + V CC x I IN
where I
LDO
is the current supplied by the internal regu-
lator, I DRV is the supply current consumed by the dri-
vers at DRV, and I IN is the supply current of the
MAX15026 without the contribution of the I DRV , as given
in the Typical Operating Characteristics . For example, in
the application circuit of Figure 5, I LDO = I DRV + I IN and
V
DRV
= V
CC
so that P
T
= V
IN
x (I
DRV
+ I
IN
).
Use the following equation to estimate the temperature
rise of the die:
T J = T A + (P T x θ
JA )
where
θ
JA is the junction-to-ambient thermal imped-
ance of the package, P
T
is power dissipated in the
device, and T A is the ambient temperature. The θ
JA is
24.4°C/W for 14-pin TDFN package on multilayer
boards, with the conditions specified by the respective
JEDEC standards (JESD51-5, JESD51-7). An accurate
estimation of the junction temperature requires a direct
measurement of the case temperature (T
C ) when actual
operating conditions significantly deviate from those
described in the JEDEC standards. The junction tem-
perature is then:
T J = T C + (P T x θ
JC )
Use 8.7°C/W as θ
JC
thermal impedance for the 14-pin
TDFN package. The case-to-ambient thermal imped-
ance (
θ
CA ) is dependent on how well the heat is trans-
ferred from the PCB to the ambient. Solder the exposed
pad of the TDFN package to a large copper area to
spread heat through the board surface, minimizing the
case-to-ambient thermal impedance. Use large copper
areas to keep the PCB temperature low.
PCB Layout Guidelines
Place all power components on the top side of the
board, and run the power stage currents using traces
or copper fills on the top side only. Make a star connec-
tion on the top side of traces to GND to minimize volt-
age drops in signal paths.
Keep the power traces and load connections short,
especially at the ground terminals. This practice is
essential for high efficiency and jitter-free operation. Use
thick copper PCBs (2oz or above) to enhance efficiency.
Place the MAX15026 adjacent to the synchronous recti-
fier MOSFET, preferably on the back side, to keep LX,
GND, DH, and DL traces short and wide. Use multiple
small vias to route these signals from the top to the bot-
tom side. Use an internal quiet copper plane to shield
the analog components on the bottom side from the
power components on the top side.
Make the MAX15026 ground connections as follows:
create a small analog ground plane near the device.
Connect this plane to GND and use this plane for the
ground connection for the V
IN bypass capacitor, com-
pensation components, feedback dividers, V
CC
capaci-
tor, RT resistor, and LIM resistor.
Use Kelvin sense connections for LX and GND to the
synchronous rectifier MOSFET for current limiting to
guarantee the current-limit accuracy.
Route high-speed switching nodes (BST, LX, DH, and DL)
away from the sensitive analog areas (RT, COMP, LIM,
and FB). Group all GND-referred and feedback compo-
nents close to the device. Keep the FB and compensation
network as small as possible to prevent noise pickup.
C
Q
V
BST
G
BST
=
∆
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