Document Outline

• Absolute Maximum Ratings
• Electrical Characteristics
• Timing Characteristics
• Miscellaneous Timing Characteristics
• Typical Operating Characteristics
• Functional Diagram
• Pin Configuration
• Pin Description
• Detailed Description
  • FSR Calibration
  • Force-Sense Resistor Signal Conditioning Interface
    • Purpose
    • Force-Sensor Characteristics
    • FSR Interface Architecture
    • Gain and Offset Range
  • Reference Generator
  • ADC
  • Flyback Boost Controller
  • Discharge Control Operational Amplifier
  • Control Scheme
  • Capacitor Fault Protection
  • UVLO (Undervoltage Lockout)
• Applications Information
  • FSR Calibration
  • Transformer Design
    • Minimum Transformer Turns Ratio
    • Primary Inductance
    • Leakage Inductance
    • Transformer Secondary Capacitance
    • Rectifying Diode
  • Detailed Pin and Operational Description
    • GSMBL
    • RESET
    • WAKEUP
    • SDA
    • SCL
    • ADD5
    • IRQ
    • VLL, VUL, VLR, and VUR
    • DGND, AGND
    • VDD
    • VDDIO
    • VBAT
    • PGND, PGND2
    • SW, SW2
    • SEC
    • VFB
    • VDRIVE, VRTN
  • Digital Interface
    • User-Accessible Address Locations
    • Hardware Configuration Register 1 (R/W): HCFG1 (0x20)
    • Hardware Configuration Register 2 (R/W): HCFG2 (0x21)
    • Scan Interval Counter Register (R/W): INTRV (0x01)
    • Press Threshold Register (R/W): PRTH (0x22)
    • VLR Calibration Register (R/W): CAL0 (0x23)
    • VLL Calibration Register (R/W): CAL1 (0x24)
    • VUR Calibration Register (R/W): CAL2 (0x25)
    • VUL Calibration Register (R/W): CAL3 (0x26)
    • Waveform Start Address Register (R/W): WVST (0x27)
    • Waveform Repetitions Register (R/W): WVREP (0x28)
    • Waveform Scaling Register (R/W): WVSCA (0x29)
    • ADC Scan Register (R/W): ADCSC (0x2A)
    • Software Reset Register (W): SRST (0x02)
    • Waveform Memory Address Pointer Register (W): WADDH (0x04) and WADDL (0x03)
    • Waveform Memory Data Register (R/W): WVDAT (0x05)
    • Flags/Status Register (R): FLAG (0x06)
    • Interrupt Mask Register (R/W): IMR (0x07)
    • FIFO Read Address Register (R): FIFOH (0x09) and FIFOL (0x08)
    • ID (Version Code) Register (R/W): IDREG (0x3F)
  • Waveform SRAM Organization
  • I2C-Compatible 2-Wire Interface
    • START (S) and STOP (P) Conditions
    • Early STOP Conditions
    • Slave Address
    • Acknowledge
    • Default Reads in I2C Mode
    • Example I2C Bus Cycles
  • FIFO Detailed Operation
  • MAX11836 Power States
    • DEEP_SLEEP
    • CHK_NXT
    • SCAN
    • DORMANT
    • WAKE
    • WAVE
    • SLEEP
• Chip Information
• Package Information