Rainbow Electronics MAX5190 - Manual (Page 10)

MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
10 ______________________________________________________________________________________
PD
(POWER-DOWN SELECT)
DACEN
(DAC ENABLE)
POWER-DOWN MODE OUTPUT STATE
0 0 Standby
MAX5187 High-Z
MAX5190 AGND
0 1 Wake-Up Last state prior to standby mode
1 X Shutdown
MAX5187 High-Z
MAX5190 AGND
Table 1. Power-Down Mode Selection
X = Don’t care
External Reference
To disable the MAX5187/MAX5190’s internal reference,
connect REN to DV
DD . A temperature-stable external ref-
erence may now be applied to drive the REFO pin to set
the full-scale output (Figure 3). Choose a reference that
can supply at least 150µA to drive the bias circuit that
generates the cascode current for the current array. For
improved accuracy and drift performance, choose a volt-
age reference with a fixed output voltage, such as the
+1.2V, 25ppm/°C MAX6520 bandgap reference.
Standby Mode
To enter the lower power standby mode, connect the
digital inputs PD and DACEN to DGND. In standby,
both the reference and the control amplifier are active
with the current array inactive. To exit this condition,
DACEN must be pulled high with PD held at DGND.
Both the MAX5187 and MAX5190 typically require 50µs
to wake up and allow both the outputs and the refer-
ence to settle.
Shutdown Mode
For lowest power consumption, the MAX5187/MAX5190
provide a power-down mode in which the reference,
control amplifier, and current array are inactive and the
DAC’s supply current is reduced to 1µA. To enter this
mode, connect PD to DV
DD . To return to active mode,
connect PD to DGND and DACEN to DV
DD
. About 50µs
are required for the parts to leave shutdown mode and
settle to their outputs’ values prior to shutdown.
Timing Information
Figure 4 shows a detailed timing diagram for the
MAX5187/MAX5190. With each high transition of the
clock, the input latch is loaded with the digital value set
by bits D7 through D0. The content of the input latch is
then shifted to the DAC register, and the output
updates at the rising edge of the next clock.
CLK
D0–D7
OUT N - 1
N - 1
N
N
N + 1
N + 1
t
DS
t DH
t CH t CL t CLK
Figure 4. Timing Diagram