Rainbow Electronics MAX5151 User Manual

Page 11

The address and control bits determine the MAX5150/
MAX5151's response, as outlined in Table 1.

The MAX5150/MAX5151's digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.

The 16-bit data can be sent as two 8-bit packets (SPI,
Microwire), with CS low during this period. The address
and control bits determine which register will be updat-
ed, and the state of the registers when exiting shut-
down. The 3-bit address/control determines the
following:

• registers to be updated

• clock edge on which data is to be clocked out via

the serial-data output (DOUT)

• state of the user-programmable logic output

• configuration of the device after shutdown.

The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.

MAX5150/MAX5151

Low-Power, Dual, 13-Bit Voltage-Output DACs

with Serial Interface

DIN

SCLK

MOSI

SCK

I/O

SPI/QSPI

PORT

+5V

CPOL = 0, CPHA = 0

MAX5150
MAX5151

Figure 3. Connections for SPI/QSPI

Figure 5. Serial-Interface Timing Diagram

SCLK

DIN

COMMAND

EXECUTED

D12 D11 D10

______________________________________________________________________________________

MSB.......Data Bits.........LSB

D12.................................D0

13 Data Bits

16 Bits of Serial Data

Control Bits

C1, C0

Address Bits

MSB ..................................................................................LSB

1 Address/2 Control Bits

Figure 4. Serial-Data Format