Omega Engineering DAQ-12 - Manual (Page 28)

4.1.4 D/A Converter 0 Register
An output to this register causes the lower twelve bits of data to be converted to an analog
output on D/A converter channel 0. The four most significant bits of data are ignored. This
register is 16-bit write only.
4.1.5 D/A Converter 1 Register
An output to this register causes the lower twelve bits of data to be converted to an analog
output on D/A converter channel 1. The four most significant bits of data are ignored. This
register is 16-bit write only.
The remaining four registers are contained in an 8254 counter/timer.
4.1.6 Clock Rate Register (low word)
The low word of the clock divider is contained in counter 0 of an 8254 counter/timer. The
output of this counter is cascaded into the input of counter 1 to produce a 32-bit timer. Mode
2 must be selected for counter 0 with a minimum count of 2. This register is 8-bit read/write.
4.1.7 Clock Rate Register (high word)
The high word of the clock divider is contained in counter 1 of the 8254 counter/timer. Mode
2 must be selected for counter 1 with a minimum count of 2. This register is 8-bit read/write.
4.1.8 Multi-Function Timer Register
The multi-function timer is implemented using counter 2 of the 8254 counter/timer. Mode
2 must be selected for this timer with a minimum count of 2. This register is 8-bit
read/write.
4.1.9 8254 Control Word/Status Register
This register is used to program the mode and report the status of the 8254 counter/timer.
This register is 8-bit read/write.
DAQ-12 Users Manual 28