C0src, Xtrig, Indx_gt – Omega Speaker Systems PCI-DAS1001 User Manual
Page 25
The table below provides a summary of bit settings and operation.
XTRIG
# Samples <1/2 FIFO,
Pre-Trigger Mode
Via SW immediately
1
1
ADHF
# Samples >1 FIFO
Pre-Trigger Mode
----------------------------------
1/2 FIFO < # Samples < 1 FIFO
Pre-Trigger Mode
Via SW when
remaining count <1024
------------------------
Via SW immediately
0
1
ADC Pacer
# Samples <1/2 FIFO
Normal Mode
Via SW immediately
1
0
ADHF
# Samples >1 FIFO
Normal Mode
----------------------------------
1/2 FIFO < # Samples < 1 FIFO
Normal Mode
Via SW when
remaining count <1024
------------------------
Via SW immediately
0
0
Sample CTR
Starts on...
FIFO Mode
ARM is set...
FFM0
PRTRG
C0SRC
This bit allows the user to select the clock source for user Counter 0.
1 = Internal 10MHz oscillator
0 = External clock source input via CTR0CLK pin on 100p connector.
READ
-
-
-
-
-
-
-
XTRIG
-
-
-
-
INDX_GT
-
-
-
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XTRIG
1 = External Trigger flip-flop has been set. This bit is write-cleared.
0 = External Trigger flip-flop reset. No trigger has been received.
INDX_GT
1 = Pre-trigger index counter has completed its count.
0 = Pre-trigger index counter has not been gated on or has not yet completed its count
.
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