Omega Engineering DIGITAL INPUT/OUTPUT PCI-DIO96 - Manual (Page 18)

GROUP 3, PORT B DATA
BADR3 + D hex
READ/WRITE
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6 7
GROUP 3, PORT C DATA
BADR3 + E hex
READ/WRITE
CL1 CL2 CL3 CL4 CH1 CH2 CH3 CH4
C1 C2 C3 C4 C5 C6 C7 C8
0 1 2 3 4 5 6 7
GROUP 3 CONFIGURE
BADR3 + F hex
READ/WRITE
CL B M1 CH A M2 M3 MS
0 1 2 3 4 5 6 7
5.4.5 8254 Configuration & Data
COUNTER 1 DATA
BADR3 + 10 hex
READ/WRITE
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6 7
The 82C54 counters 1 and 2 have been configured in hardware to produce a 32-bit
counter for use in interrupt generation. This register provides access to the lower 16
data bits. Since the interface to the 82C54 is only 8-bits wide, write counter data in
two bytes; low byte first, followed by the high byte.
COUNTER 2 DATA
BADR3 + 11 hex
READ/WRITE
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6 7
The 82C54 counters 1 and 2 have been configured in hardware to produce a 32-bit
counter for use in interrupt generation. This register provides access to the upper 16
data bits. Since the interface to the 82C54 is only 8-bits wide, write counter data in
two bytes; low byte first, followed by the high byte.
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