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Renesas M65881AFP User Manual

Page 6

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Rev.1.00 2003.05.08 page 6 of 23

M65881AFP

PIN DESCRIPTION

Pin No.

Name

I/O

Output

Current
on 3.3V

Signal Level

1

VddL

Power Supply for Lch PWM Power Stage (3.3V)

2

OUTL1

O

Lch PWM1 Output for Power Stage

3.3V

3

VssL

GND for Lch PWM Power Stage

4

OUTL2

O

Lch PWM2 Output for Power Stage

3.3V

5

XOVdd

Power Supply for Secondary Master Clock Buffer ( 3.3V )

6

XfsoOUT

O

Buffered Output of Secondary Master Clock (1024/512fso)

2mA

3.3V

7

XOVss

GND for Secondary Master Clock Buffer

8

DVdd

Power Supply for Digital Block (1.8V)

9

DVss

GND for Digital Block

10

MCKSEL

I

Secondary Master Clock Selector "L":1024fso, "H":512fso

3.3V

11

SCDT

I

Serial Control • Data Input

3.3V

12

SCSHIFT

I

Serial Control • Shift Clock Input

3.3V

13

SCLATCH

I

Serial Control • Latch Signal Input

3.3V

14

NSPMUTE

I

PWM Duty 50% Mute ( "L": Active )

3.3V

15

INIT

I

Initialize Input ( Power Supply Reset ) ; "L" : Reset, "H" : Release

3.3V

16

LRCK

I

LRCK Input (PCM Signal )

3.3V

17

BCK

I

BCK Input ( PCM Signal )

3.3V

18

DATA

I

DATA Input ( PCM Signal )

3.3V

19

BFVdd

Power Supply for Input/Output 3.3V Buffer

20

BFVss

GND for Input/Output 3.3V Buffer

21

XfsiIN

I

Primary Master Clock Input (256fsi/512fsi )

3.3V

22

FsoCKO

O

Secondary Fso Clock Output

4mA

3.3V

23

FsoI

I

Secondary Fso Clock Input

3.3V

24

SFLAG

O

Asynchronous Flag ( H: Active )

4mA

3.3V

25

TEST2

I

Test2 must be connected to GND

3.3V

26

TEST1

I

Test1 must be connected to GND

3.3V

27

HPOUTR2

O

Rch PWM2 Output for Headphone

3.3V

28

HPVssR

GND for Rch Headphone

29

HPOUTR1

O

Rch PWM1 Output for Headphone

3.3V

30

HPVddR

Power Supply for Rch Headphone ( 3.3V )

31

HPOUTL2

O

Lch PWM2 Output for Headphone

3.3V

32

HPVssL

GND for Lch Headphone

33

HPOUTL1

O

Lch PWM1 Output for Headphone

3.3V

34

HPVddL

Power Supply for Lch Headphone ( 3.3V )

35

XVss

GND for Secondary Master Clock Input Buffer

36

XfsoIN

I

Secondary Master Clock Input (1024fso/512fso)

3.3V

37

XVdd

Power Supply for Secondary Master Clock Buffer ( 3.3V )

38

VssLR

GND for PWM Power Stage

39

OUTR2

O

Rch PWM 2 Output for Power Stage

3.3V

40

VssR

GND for Rch PWM Power Stage

41

OUTR1

O

Rch PWM 1 Output for Power Stage

3.3V

42

VddR

Power Supply for Rch PWM Power Stage ( 3.3V)

Description