Renesas M65881AFP - Manual (Page 19)

Rev.1.00 2003.05.08 page 19 of 23
M65881AFP
Flag to " Enable " of Asynchronous Detection for secondary block ( bit8: ASYNCEN2)
ASYNCEN2 (bit8 ) controls " Enable" and " Disable" for secondary asynchronous detector.
"L“ … "disable"
"H" … "enable“
Under condition of ASYNCEN2="L", secondary side asynchronous detection is in-effective
under asynchronous position, whether Fsol Clock is not inputted, there by M65881AFP does not
operate function for instance mute operation.
Reverse Lch/Rch for PWM Output pins (bit9: CHSEL)
* Enable to control for both PWM for Power and Headphone.
"L" … As it is aligned
"H" … Reverse to pin alignment of Lch/Rch
∆Σ
Rch Input Phase (bit10: DRPOL)
"L"…. Same phase ( "Through")
"H"….This setting makes
∆Σ
Rch Input in reverse, further makes PWM block input phase reverse,
ultimately phase becomes positive phase ( Input pin and Output pin's phase is same ).
Sampling rate converter block reset ( Initialize function ) (bit11: SRCRST)
"L" …..normal operation
"H" to "L" edge…..Reset ( Initialize function )
Reverse for R1 and R2 of Output pins. (bit12:CHRSEL).
“L”… As it is aligned
"H"..…Reverse to pin alignment of R1/R2.
Zero Mute of a gain control input (bit13:GIMUTE)
"L" …Mute release H… Mute
Duty 50% Mute of PWM Output (bit14: NSPMUTE)
Fixed PWM duty 50% Mute
"L"…..Mute release
"H"….. Mute
This function exists also in a pin by the same name.
(This Mute function can be set either NSPMUTE flag or NSPMUTE pin.)
Refer to Page13 about a relation with the gain control mode of serial control bit9 and bit 10
(LR independent control).
G-Mute for PWM Output Data (bit15: PGMUTE ) *Enable to PWM both PWM for Power and Headphone.
At G-MUTE flag = H , PGMUTE pin fixes each PWM Output as followings.
"L"….. Mute release
"H"….. Fixed Mute for PWM Output ( Fixed value as follows )
L1,L2,R1 and R2 : "L" fixed
< PWM Output for Headphone, Serial control (system1 mode; bit24) PWMHP="L">
L1,L2,R1 and R2 : "H“ fixed
< PWM Output for Headphone, Serial control (system1 mode; bit24) PWMHP="H">
L1, R1 : "L" fixed
L2, R2 : "H" fixed
∆Σ
: operating rate (bit16 : NSSPEED) Refer to the Table 3-3
"L" … 16fso
"H" … 32fso *Enable only MCKSEL="L"(1024fso), NSOBIT="H“
(Except for this condition, Operating rate automatically becomes 16fso ).
∆Σ
: The setting of bit length (bit17 : NSOBIT) Refer to the Table 3-3.
NSOBIT selects bit length for
∆Σ
operation. This is set by force as 5bit at MCKSEL="H".
"L" … 6bit (63 value)
"H" … 5bit (31value)
∆Σ
: DC dithering Rch Phase (bit18:DCDRPOL)
"L"…Same phase “H"…Reverse phase
∆Σ
: DC dithering selection (bit19, 20 : DCDSEL0,1 ) Refer to the Table 3-1.
∆Σ
:AC dithering Rch Phase (bit21 : ACDRPOL)
"L"…Same phase “H"…Reverse phase
∆Σ
: AC dithering selection (bit22, 23, 24 : ACDSEL0, 1, 2) Refer to the Table 3-2.