NEC A1160 - Manual (Page 23)

Memory
2-5
Figure 2-3 Node Controller
Memory
Express5800/A1160 systems use a directory-based cache-coherent memory system.
The directory-based memory tracks ownership of data. The cache coherency protocols
force the processor cache components and main storage components to
y Keep track of all copies of a cache line.
y Determine which processor has permission to update an instance of a cache line.
y Mark other copies of the cache line as "invalid" when an update occurs.
Memory Board. System memory is contained on the memory board. The memory board
includes the fully buffered DIMMs and their associated power delivery components. A
cell contains one or two memory boards. Each memory board supports
y Two fully buffered DIMM channels from the node controller. Each channel operates
as a single memory channel. These two channels are referred to as a channel pair.