LSI SAS3041E User Manual
Page 19
PCI Performance
1-5
Version 1.0
Copyright © 2006 by LSI Logic Corporation. All rights reserved.
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Contains a replay buffer that preserves a copy of the data for
retransmission in case a CRC error occurs
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Supports the PCI Express Advanced Error Reporting capabilities
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Uses a packetized and layered architecture
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Achieves a high bandwidth per pin with low overhead and low latency
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PCI Express is software compatible with PCI and PCI-X software
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Leverages existing PCI device drivers
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Supports the Memory, I/O, and Configuration address spaces
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Supports memory read/write transactions, I/O read/write
transactions, and configuration read/write transactions
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Provides 4 Kbytes of PCI Configuration address space per device
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Supports posted and non-posted transactions
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Provides quality of service (QOS) link configuration and arbitration
policies
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Supports Traffic Class 0 and one virtual channel
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Supports Message Signaled Interrupts (both MSI and MSI-X) as well
as INTx interrupt signaling for legacy PCI support
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Supports end-to-end CRC (ECRC) and Advanced Error Reporting