SMSC 1.8V IO Voltage (10%) flexPWR USB3310 - Manual (Page 6)

Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock
Revision 1.11 (10-31-08) 6 SMSC USB3310 REV C
PRODUCT PREVIEW
19
A4
DIR
Output,
CMOS
N/A Controls the direction of the data bus.
When the PHY has data to transfer to the
Link, it drives DIR high to take ownership
of the bus. When the PHY has no data to
transfer it drives DIR low and monitors
the bus for commands from the Link.
20
A3
STP Input,
CMOS
High The Link asserts STP for one clock cycle
to stop the data stream currently on the
bus. If the Link is sending data to the
PHY, STP indicates the last byte of data
was on the bus in the previous cycle.
21
B3
VDD1.8 Power N/A External 1.8V Supply input pin. This pad
needs to be bypassed with a 0.1uF
capacitor to ground, placed as close as
possible to the USB3310.
22
B2
RESETB Input,
CMOS,
N/A When low, the part is suspended with all
of the I/O tri-stated. When high the
USB3310 will operate as a normal ULPI
device.
23
A2
REFCLK Input,
CMOS
N/A Reference Clock input.The required
frequency is configured by the
REFSEL[1:0] pins.
24
A1
RBIAS Analog,
CMOS
N/A Rbias pin. This pin requires an 8.06k Ω
(±1%) resistor to ground, placed as close
as possible to the USB3310.
FLAG
C3
GND Ground N/A Ground.
QFN only: The flag should be connected
to the ground plane with a via array
under the exposed flag. This is the main
ground for the IC.
Table 1 USB3310 Pin Description (continued)
PIN
BALL NAME
DIRECTION/
TYPE
ACTIVE
LEVEL DESCRIPTION