SMSC LAN9500 User Manual
Datasheet, Product features
SMSC LAN9500/LAN9500i
Revision 1.7 (10-02-08)
DATASHEET
Datasheet
PRODUCT FEATURES
LAN9500/LAN9500i
Hi-Speed USB 2.0 to 10/100
Ethernet Controller
Highlights
Single Chip Hi-Speed USB 2.0 to 10/100 Ethernet
Controller
Integrated 10/100 Ethernet MAC with Full-Duplex
Support
Integrated 10/100 Ethernet PHY with HP Auto-MDIX
support
Integrated USB 2.0 Hi-Speed Device Controller
Integrated USB 2.0 Hi-Speed PHY
Implements Reduced Power Operating Modes
Target Applications
Embedded Systems
Set-Top Boxes
PVR’s
CE Devices
Networked Printers
USB Port Replicators
Standalone USB to Ethernet Dongles
Test Instrumentation
Industrial
Key Benefits
USB Device Controller
—
Fully compliant with Hi-Speed Universal Serial Bus
Specification Revision 2.0
—
Supports HS (480 Mbps) and FS (12 Mbps) modes
—
Four endpoints supported
—
Supports vendor specific commands
—
Integrated USB 2.0 PHY
—
Remote wakeup supported
High-Performance 10/100 Ethernet Controller
—
Fully compliant with IEEE802.3/802.3u
—
Integrated Ethernet MAC and PHY
—
10BASE-T and 100BASE-TX support
—
Full- and half-duplex support
—
Full- and half-duplex flow control
—
Preamble generation and removal
—
Automatic 32-bit CRC generation and checking
—
Automatic payload padding and pad removal
—
Loop-back modes
—
TCP/UDP/IP/ICMP checksum offload support
—
Flexible address filtering modes
–
One 48-bit perfect address
–
64 hash-filtered multicast addresses
–
Pass all multicast
–
Promiscuous mode
–
Inverse filtering
–
Pass all incoming with status report
—
Wakeup packet support
—
Integrated Ethernet PHY
–
Auto-negotiation
–
Automatic polarity detection and correction
–
HP Auto-MDIX support
–
Link status change wake-up detection
—
Support for 3 status LEDs
—
External MII and Turbo MII support HomePNA™ and
HomePlug® PHY
Power and I/Os
—
Various low power modes
—
11 GPIOs
—
Supports bus-powered and self-powered operation
—
Integrated power-on reset circuit
—
External 3.3v I/O supply
–
Internal 1.8v core supply regulator
Miscellaneous Features
—
EEPROM Controller
—
IEEE 1149.1 (JTAG) Boundary Scan
—
Requires single 25 MHz crystal
Software
—
Windows XP/Vista Driver
—
Linux Driver
—
Win CE Driver
—
MAC OS Driver
—
EEPROM Utility
Packaging
—
56-pin QFN (8x8 mm) Lead-Free RoHS Compliant
package
Environmental
—
Commercial Temperature Range (0°C to +70°C)
—
Industrial Temperature Range (-40°C to +85°C)
Document Outline
- Chapter 1 Introduction
- Chapter 2 Pin Description and Configuration
- Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW)
- Table 2.1 MII Interface Pins
- Table 2.2 EEPROM Pins
- Table 2.3 JTAG Pins
- Table 2.4 Miscellaneous Pins
- Table 2.5 USB Pins
- Table 2.6 Ethernet PHY Pins
- Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad
- Table 2.8 No-Connect Pins
- Table 2.9 56-QFN Package Pin Assignments
- 2.1 Buffer Types
- Chapter 3 EEPROM Controller (EPC)
- Chapter 4 Operational Characteristics
- 4.1 Absolute Maximum Ratings*
- 4.2 Operating Conditions**
- 4.3 Power Consumption
- 4.4 DC Specifications
- 4.5 AC Specifications
- 4.6 Clock Circuit
- Chapter 5 Package Outline
- Chapter 6 Revision History