SMSC USB3280 - Manual (Page 37)

Hi-Speed USB Device PHY with UTMI Interface
Datasheet
SMSC USB3280 37 Revision 1.5 (11-15-07)
DATASHEET
To detect the assertion of the downstream Chirp K's and Chirp J's for 2.5us {T
FILT
}, the SIE must see
the appropriate LINESTATE signals asserted continuously for 165 CLKOUT cycles.
Figure 8.6 HS Detection Handshake Timing Behavior from Suspend
Table 8.8 HS Detection Handshake Timing Values from Suspend
TIMING
PARAMETER DESCRIPTION VALUE
T0 While in suspend state an SE0 is detected on the USB. HS
Handshake begins. D+ pull-up enabled, HS terminations
disabled, SUSPENDN negated. 0 (HS Reset T0)
T1 First transition of CLKOUT. CLKOUT "Usable" (frequency
accurate to ±10%, duty cycle accurate to 50±5). T0 < T1 < T0 + 5.6ms
T2 Device asserts Chirp K on the bus. T1 < T2 < T0 + 5.8ms
T3 Device removes Chirp K from the bus. (1 ms minimum width)
and begins looking for host chirps. T2 + 1.0 ms < T3 <
T0 + 7.0 ms
T4 CLK "Nominal" (CLKOUT is frequency accurate to ±500
ppm, duty cycle accurate to 50±5). T1 < T3 < T0 + 20.0ms
CLK60
Look for host chirps Device Chirp K
SUSPENDN
DP/DM
TERMSELECT
TXVALID
SE0
J
CLK power up time
XCVRSELECT
OPMODE 1
OPMODE 0
time
T0 T3 T4 T1 T2