Intel 8XC251SA - Manual (Page 29)

PRELIMINARY
29
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Figure 14. External Bus Cycle: Data Write (Nonpage Mode)
Figure 15. External Bus Cycle: Code Fetch/Data Read (Page Mode)
A0-A7
WCLK
ALE
WR#
T
WLYV
WAIT#
P0
P2
A5002-01
State 1 State 2 State 3 State 4
T
CLYX
min
T
CLYV
D0-D7 stretched
A8-A15 stretched
WR# stretched
T
WLYX
max
T
WLYX
min
T
CLYX
max
A8-A15
WCLK
ALE
RD#/PSEN#
WAIT#
P2
P0 A0-A7
A5001-01
State 1 State 2 State 3 State 1 (next cycle)
T
CLYX
min
T
CLYV
A8-A15 D0-D7 stretched
A0-A7 stretched
RD#/PSEN# stretched
T
CLYX
max
T
RLYV
T
RLYX
max
T
RLYX
min