Intel 8XC251SA - Manual (Page 25)

PRELIMINARY
25
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.3.2 EXTERNAL BUS CYCLES, PAGE MODE
Figure 10. External Bus Cycle: Code Fetch (Page Mode)
XTAL1
ALE
TLHLL
†
A15:8 D7:0
TRHDZ1
RD#/PSEN#
P2
P0/A16/A17
TRHDX
TLLRL
†
TAVLL
†
TRLDV
†
TRLAZ
TAVRL
†
TAVDV1
†
TAVDV2
†
TOSC
A4213-02
TLHAX
†
Instruction In
A7:0/A16/A17
D7:0
Instruction In
A7:0/A16/A17
Page Miss
††
Page Hit
††
TAVDV3
† The value of this parameter depends on wait states. See the table of AC characteristics.
†† A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one
state (2T
OSC
); a page miss requires two states (4T
OSC
).
††† During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
TLLAX
†††