IBM 560 - Manual (Page 133)

microprocessor (continued)
cache memory operation 2-2
mode switch compatibility 2-28
performance 1-8
real address mode
2-28
specifications 1-3, 1-8
mode switch, protected 2-28
model identifier 1-2
model/submodel bytes 1-2
description 2-2
model identifier
1-2
mouse
connector 2-4
signals 2-4
N
NMI (nonmaskable interrupt) 2-26
O
output protection, power
supply 1-12
output voltage sequencing 1-12
overvoltage fault 1-12
P
page hit 1-8
page miss 1-8
parallel controller port 1-4
parity check enable 2-27
password, power-on 2-29
PCMCIA 3-7
interface 1-7
slots 1-4, 3-7
subsystem 3-7
Pentium 90/120MHz 1-3
performance, system 1-8
ports
parallel 1-4
serial 1-4
system 2-26
POST
cache test 2-2
error codes 2-31
POST (continued)
memory errors 2-14
parity check 2-26
password 2-29
reset 2-28
ROM test
2-13
power
cable 1-9
loss 2-21
power supply 1-11
battery pack (lithium ion) 1-13
connector 1-12
output protection
1-12
output voltages 1-11
outputs 1-11
voltage sequencing
1-12
power-on password 2-29
power-on self-test (POST)
cache test 2-2
error codes 2-31
memory errors 2-14
parity check 2-26
password 2-29
reset 2-28
ROM test
2-13
protected mode switch 2-28
R
RAM (random access
memory) 2-13
I/O operations, RT/CMOS 2-18
subsystem 2-13
RAM subsystem 1-3
read-only memory (ROM) 1-3, 2-13
real mode switch 2-28
real-time clock 2-16
bytes, RT/CMOS 2-19
refresh rate, specifications 1-8
refresh request 2-27
registers
miscellaneous system 2-26
RT/CMOS address and NMI
mask 2-17
RT/CMOS data 2-17
RT/CMOS status 2-21
Index X-3