Motorola 68HC08LD - Manual (Page 8)

 iSYSTEM, March 2004 8/12
General HC08 Emulation Notes
Internal RAM, Internal EEPROM
Note that the internal RAM of the 68HC08 CPU on the POD is disabled during the emulation. Thereby,
associated memory area must be mapped as emulator RAM by the user. If the CPU provides a capability to write
to the internal RAM or EEPROM via memory window (no specific programming sequence required), the
download file can be loaded to the internal RAM or EEPROM using the ‘Target Download’ option. The
debugger downloads the code to the internal memory after reset via the CPU. If the CPU (e.g. 68HC08AZ60A)
requires some registers to be configured before the CPU is able to write in the EEPROM area, the user must
configure the necessary registers respectively, using the initialization dialog. Any sequence, added in the
initialization dialog, is executed immediately after reset, before the download is performed. Note that some
HC08 derivatives (e.g. 68HC908AB32) don't allow writing to the internal EEPROM area via memory window
since a special programming sequence is required. Consequently, the download file cannot be loaded to the
internal EEPROM by the debugger. Therefore, the programming algorithm must be implemented by the user in
his application. Refer to the CPU datasheets for more details.
Note that debugging is limited while executing the program in the internal EEPROM. At the HC08 family, the
internal RAM is disabled during the emulation and the associated memory area overlaid by the in-circuit
emulator (ICE). Thus, the debugging in the CPU internal RAM area has no limitations.
While the CPU accesses internal memory resources, the (ICE) loses the control over the CPU since the external
bus is not active. Therefore, breakpoints cannot be set and the user's program cannot be stopped or stepped when
executing in the internal EEPROM. Additionally, debug windows cannot be updated as well.
Normally, in the target application the CPU executes the program in the internal or external ROM. Using the
ICE, ROM memory is overlaid by the emulation memory and consequently the program can be debugged
without restrictions. But sometimes there is a need to execute some short routines in the CPU internal memory.
Using the ICE, the user can run such a routine, but cannot debug it.
Checksum
When performing any kind of checksum in the emulated (code) area, note that all breakpoints must be removed
before, otherwise the results are distorted. Note that the emulator forces "breakpoint" instruction on the data bus
when executing the code at the address where breakpoint is set.
COP
Using any HC08 POD, the CPU's internal COP must be either disabled in the CONFIG-1 register (if the CPU
has such an option) or serviced by the user's program, otherwise the emulation fails. While the user’s program is
stopped, the debugger updates the COP counter.
COP servicing by the user's program
Writing any value to location 0xFFFF before overflow occurs clears the COP counter and prevents reset. A user
must be careful since reset vector and COP register are located at the same address.
COP update routine should be placed in the main program and not in an interrupt subroutine. Such an interrupt
subroutine could keep the COP from generating a reset even while the main program is not working properly.
Clock
Clock source can be either used internal from the emulator or external from the target. It is recommended to use
the internal clock when possible. When using the clock from the target, it may happen that the emulator cannot
initialize any more.
Internal CPU Flash
Internal FLASH is overlaid by the emulation memory and disabled during the emulation and cannot be used in
any way.