Motorola M6800 User Manual

Page 8

MPU-8

MPU Signal Descriptions

1. READ/WRITE (R/W):

This output line is used to signal all devices external to

the MPU that the MPU is in a read state (R/W = High) or a

write state (R/W = Low). The normal standby state of this

line when no external devices are being accessed is a high

state. This line is three-state. When three-state goes

high, this line enters the high impedance mode.

2. VALID MEMORY ADDRESS(VMA):

This output line, (when in the high state) tells all

devices external to the MPU that there is a valid address

in the address bus. For RAM's and ROM's, this line should

be ANDed with 12 clock and used as one of the enables. For

PIA's, this line should be ANDed with one of the PIA

address lines. This signal is not three-state.

3. DATA BUS ENABLE(DBE):

This signal will enable the data bus drives when in the

high state. This input is normally the phase 2 (12) clock.

During the high state, it will permit data to be output

during a write cycle. During an MPU read cycle, the data

bus drives will be disabled internally.

4. INTERRUPT REQUEST(IRQ):

This input from the PIA's requests that an interrupt

sequence be generated within the machine. The processor

will wait until it completes the current instruction that

is being executed before it recognizes the request. At that

time, if the interrupt mask bit in the Condition Code

begin an interrupt sequence. The Index Register, Program