Motorola M6800 - Manual (Page 18)

MPU-18
NMI SEQUENCE
1. If NMI goes low for at least one Ø2 cycle, the MPU will wait for
completion of current instruction.
2. The internal registers PC, X, A, B and CC will then be stored in RAM at
the address indicated by the stack pointer in descending locations (7
bytes in all).
3. The IRQ (bit I = 1) mask is set.
4. Data at FFFC is loaded into PCH.
5. Data at FFFD is loaded into PCL.
6. PC contents go out on ADRS bus during Ø1.
7. Contents of cell addressed enters instruction register during Ø2 and is
decoded as first instruction of NMI subroutine.
8. If two or more byte instruction, additional bytes enter MPU for execution.
If not, go to next step.
9. After execution, Step 5 is repeated for subsequent instructions. This loop
is repeated until the instruction "RTI" is executed.
RTI EXECUTION
1. The contents of the stack are loaded back into the MPU. (unwinds)
2. The contents of the PC go out on the address bus to fetch the first byte
of the next instruction.