Motorola M6800 - Manual (Page 17)

MPU-17
IRQ SEQUENCE
1. If bit "I" in condition code register is not set (I = 0) and IRQ goes low
for at least one Ø2 cycle, the IRQ sequence will be entered.
2. After completion of the current instruction, internal registers PC, X, A,
B and CC will be stored in RAM at the address indicated by the stack
pointer in descending locations (7 bytes in all).
3. The IRQ mask (bit I = 1) is set.
4. Data at FFF8 gets loaded into PCH.
5. Data at FFF9 gets loaded into PCL.
6. PC contents go out on address bus during
7. Contents of call addressed enters instruction register during Ø2 and is
decoded as first instruction of interrupt routine.
8. If it is a more than 1 byte instruction, additional bytes enter MPU for
execution. If not, go to next step.
9. After execution, step 5 is repeated for subsequent instructions. This loop
is repeated until the instruction "RTI" is executed.