FUJITSU MHA2032AT - Manual (Page 64)

5.1 Physical Interface
C141-E042-01EN 5-3
Table 5.1 Signal assignment on the interface connector
Pin No. Signal Pin No. Signal
A
C
E
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
ENCSEL
ENCSEL
(KEY)
RESET–
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
GND
DMARQ
IOW–
IOR–
IORDY
DMACK–
INTRQ
DA1
DA0
CS0–
DASP–
+5 VDC
GND
B
D
F
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
GND
MSTR
(KEY)
GND
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
(KEY)
GND
GND
GND
CSEL
GND
IOCS16–
PDIAG
DA2
CS1–
GND
+5 VDC
unused
[signal] [I/O] [Description]
ENCSEL I This signal is used to set master/slave using the CSEL signal (pin 28).
Pins A and C Open: Sets master/slave by the MSTR signal
without using the CSEL signal.
Short: Sets master/slave using the CSEL signal.
The MSTR signal is ignored.