FUJITSU MHZ2250BJ - Manual (Page 67)

4.6 Read/write Circuit
4.6.3 Read circuit
The head read signal from the PreAMP is regulated by the automatic gain control
(AGC) circuit. Then the output is converted into the sampled read data pulse by
the programmable filter circuit and the flash digitizer circuit. This signal is
converted into the read data by the decoder circuit based on the read data
maximum-likelihood-detected by the Viterbi detection circuit.
(1) AGC circuit
The AGC circuit automatically regulates the output amplitude to a constant value
even when the input amplitude level fluctuates. The AGC amplifier output is
maintained at a constant level even when the head output fluctuates due to the
head characteristics or outer/inner head positions.
(2) Programmable filter circuit
The programmable filter circuit has a low-pass filter function that eliminates
unnecessary high frequency noise component and a high frequency boost-up
function that equalizes the waveform of the read signal.
Cut-off frequency of the low-pass filter and boost-up gain are controlled from the
register in read channel block. The MPU optimizes the cut-off frequency and
boost-up gain according to the transfer frequency of each zone.
(3) FIR circuit
This circuit is 10-tap sampled analog transversal filter circuit that equalizes the
head read signal to the Modified Extended Partial Response (MEEPR) waveform.
(4) A/D converter circuit
This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital
Read Data.
(5) Viterbi detection circuit
The sample hold waveform output from the flash digitizer circuit is sent to the
Viterbi detection circuit. The Viterbi detection circuit demodulates data according
to the survivor path sequence.
4.6.4 Digital PLL circuit
The drive uses constant density recording to increase total capacity. This is
different from the conventional method of recording data with a fixed data transfer
rate at all data area. In the constant density recording method, data area is divided
into zones by radius and the data transfer rate is set so that the recording density of
the inner cylinder of each zone is nearly constant. The drive divides data area into
30 zones to set the data transfer rate.
The MPU set the data transfer rate setup data (SD/SC) to the RDC block that
includes the Digital PLL circuit to change the data transfer rate.
C141-E280 4-11