Fpga resources, Interrupts, Communication ports – Sundance SMT395E User Manual
Page 14: Sdb clock selection, Global bus, Config & nmi, Timer
Version 2.1
Page 14 of 30
SMT395Q User Manual
FPGA resources
Interrupts
See
Communication ports
The SMT395E provides 4 ComPorts. They are ComPort 0, 1, 3, and 4.
See
SDB
The SMT395E provides two SHB which are 32-bit SDB.
They are numbered SDB_0 for SHB_A, SDB_1 for SHB_B.
See
SDB Clock selection
The SDB clock selection is not implemented. The clock is running at the EMIF speed i.e.
120MHz.
RSL
This interface is still under test. It needs to be standardized across the Sundance module
range.
The status so far:
-5 FPGA are limited to 2Gb/s serial links (see Xilinx datasheet).
-6 FPGA theoretical limit is 3.125Gb/s. This has not been verified on the hardware yet.
Tests have been performed with aurora protocol with on-board 100MHz clock. A single lane
solution gives around 170MB/s between DSPs. The first tests on the 4 lanes interface have
been performed and we are evaluating the best architecture.
The board also includes a differential oscillator (EG-2121CA LV-PECL) for faster speed rate.
The interface is not fixed and not provided yet.
Global bus
The SMT395E provides one global bus interface.
See
CONFIG & NMI
See
Timer
See