Sundance SMT395E - Manual (Page 10)

Version 2.1 Page 10 of 30 SMT395Q User Manual
Boot Mode
The SMT395E is configured to boot from flash after a reset.
Flash Boot
1. The processor copies a bootstrap program from the first part of the flash memory into
internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT395E then performs the following
operations:
1. All relevant C60 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the ComPorts,
the Global bus and the Sundance High-speed Buses. This step must have been
completed before data can be sent to the ComPorts from external sources such as
the host or other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the four ComPorts
until data appears on one of them. The bootstrap will then load a program in boot
format from that port; the loader will not read data arriving on other ports. See
“Application Development” for details of the boot loader format;
4. Finally, control is passed to the loaded program.
The delay between the release of the board reset and the FPGA configuration is around
2s for a SMT395E.
A typical time to wait after releasing the board reset should be in excess of this delay, but
no damage will result if any of the I/Os are used before they are fully configured. In fact,
the ComPorts will just produce a not ready signal when data is attempted to be
transferred during this time, and then continue normally after the FPGA is configured.