Sundance SMT395E - Manual (Page 12)

User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001
SDRAM
The DSP has access to 128MBytes of SDRAM. The SDRAM operates at the EMIF clock
speed. It is typically 120MHz for the SMT395E.
It has 128MBytes with 64MBytes at address 0x80000000, and 64MBytes at 0x90000000.
FLASH
An 8MBytes flash memory is provided with direct access by DSP_A. This device contains
boot code for the DSP_A and the configuration data for the FPGA.
This is a 16-bit wide device.
The flash device can be re-programmed by the DSP at any time. There is a software
protection mechanism to stop most errant applications from destroying the device’s contents.
Note that the flash memory is connected as a 16-bit device, but during a C6x boot (internal
function of the C6x) only the bottom 8 bits are used.
As the C60 only provides 20 address lines on its EMIF_B, two GPIO lines (9 and 10) are
used to access this device. So the device should be seen as divided in 4x 2MBytes pages.
FLASH Paging
Selecting the visible flash memory page (4 pages of 2MBytes) involves setting up the GPIO
registers bits 9 and 10. Make sure that the setup of the other GPIO is kept untouched as
they are used for external interrupt, and LEDs.