Sundance SMT395E - Manual (Page 13)

Version 2.1 Page 13 of 30 SMT395Q User Manual
Virtex-II Pro FPGA
This device, Xilinx XC2VP70, is responsible for the provision of the SHBs, RSLs, 4 ComPorts
and the Global bus. On power-up, this device is un-configured (SRAM based FPGA
technology). During the DSP boot process, the FPGA is configured for normal operation
from the Flash ROM.
Note that the ComPorts and Global bus interfaces provided by the FPGA are NOT 5V
tolerant and can thus not be interfaced with older systems using the ‘C40 based modules
and TIM carriers.
All of the external interfaces provided by the FPGA are fully described in the SMT6400 help
file.
The Sundance High-speed BUS (SHB) specification can be found here .
The SDL specification can be found here .
The RSL specification (Xilinx Rocket IO) can be found here .
The FPGA configuration is done in two steps:
First asserting the prog line clears the FPGA configuration. This is simply done by an access
in EMIF_B CE2.
Then after the FPGA configuration has cleared the FPGA configuration is programmed
serially by writing the data from the flash in EMIF_B CE3.
At the end of the programming a register is polled to wait until the FPGA is configured and
proceed with the application loading process.
External Clock
An external clock input is provided to the FPGA. This signal is directly connected to the
secondary TIM connector user defined pin 12.
Version control
Version number for FPGA firmware and boot code is stored in the Flash ROM during
programming as zero-terminated ASCII strings. These are displayed when using the
SMT6001 utility.
Reprogramming the firmware and boot code
The reprogramming of the module is done using the SMT6001 .
It contains the latest boot code and FPGA firmware for it and allows storing a user
application in it.