Advantech AIMB-766 - Manual (Page 58)

AIMB-766 User Manual 46
3.3.1 CPU Configuration
Figure 3.5 CPU Configuration Setting
Ration CMOS Setting
Sets the ratio between CPU core clock and the FSB Frequency.
Hardware Prefetcher
Hardware Prefetcher is a technique that fetches instructions and/or data from mem-
ory into the CPU cache memory well before the CPU needs it, so that it can improve
the load-to-use latency. You may choose to enable or disable it.
Adjacent Cache Line Prefetch
The Adjacent Cache-Line Prefetch mechanism, like automatic hardware prefetch,
operates without programmer intervention. When enabled through the BIOS, two 64-
byte cache lines are fetched into a 128-byte sector, regardless of whether the addi-
tional cache line has been requested or not. You may choose to enable or disable it.
Max CPUID Value Limit
This is disabled for Windows XP.
Execute Disable Bit
This item specifies the Execute Disable Bit Feature. The settings are Enabled and
Disabled. The Optimal and Fail-Safe default setting is Enabled. If Disabled is
selected, the BIOS forces the XD feature flag to always return to 0.
PECI
You may choose to disable or enable the Platform Environment Control Interface
function.