IBM POWERPC 750GL - Manual (Page 253)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_07.fm.(1.2)
March 27, 2006 Signal Descriptions
Page 253 of 377
Address Bus Busy (ABB)—Input
7.2.2 Address Transfer Start Signals
Address transfer start signals are input and output signals that indicate that an address-bus transfer has
begun. The transfer start (TS) signal identifies the operation as a memory transaction.
For detailed information about how TS interacts with other signals, see Section 8.3.2, Address Transfer, on
page 292.
7.2.2.1 Transfer Start (TS)
The TS signal is both an input and an output signal on the 750GX.
Transfer Start (TS)—Output
Transfer Start (TS)—Input
State Asserted Indicates that another master is the current address-bus owner.
Negated Indicates that the address bus might be available for use by the 750GX (see
BG).
The 750GX will also track the state of ABB on the bus from the TS and
AACK inputs. (See Section 8.3.1, Address-Bus Arbitration, on page 290.)
Timing Assertion Must occur whenever the 750GX must be prevented from using the address
bus.
Negation May occur whenever the 750GX can use the address bus.
State Asserted Indicates that the 750GX has begun a memory bus transaction, and that the
address-bus and transfer attribute signals are valid. When asserted with the
appropriate TT[0–4] signals, it is also an implied data-bus request for a
memory transaction (unless it is an address-only operation).
Negated Indicates that a bus transaction is not being started.
Timing Assertion Occurs on the first cycle of ABB assertion.
Negation Occurs one bus clock cycle after TS is asserted.
High
Impedance Occurs the bus cycle following AACK (same cycle as ABB negation).
State Asserted Indicates that another master has begun a bus transaction, and that the
address-bus and transfer attribute signals are valid for snooping (see
Section 7.2.4.6, Global (GBL), on page 261.
Negated Indicates that a bus cycle is not being started.
Timing Assertion/
Negation Must be asserted for one cycle only, and then immediately negated. Asser-
tion may occur at any time during the assertion of ABB.