IBM POWERPC 750GL - Manual (Page 252)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Signal Descriptions
Page 252 of 377
gx_07.fm.(1.2)
March 27, 2006
7.2.1.2 Bus Grant (BG)—Input
7.2.1.3 Address Bus Busy (ABB)
The address bus busy (ABB) signal is both an input and an output signal.
Address Bus Busy (ABB)—Output
State Asserted Indicates that the 750GX may, with proper qualification, assume mastership
of the address bus. A qualified bus grant occurs when BG is asserted and
ABB and ARTRY are not asserted on the bus cycled following the assertion
of AACK.
Note that the assertion of BR is not required for a qualified bus grant (to allow
bus parking).
Negated Indicates that the 750GX is not granted next address-bus ownership.
Timing Assertion May occur on any cycle. Once the 750GX has assumed address-bus owner-
ship, it will not begin checking for BG again until the cycle after AACK.
Negation Must occur whenever the 750GX must be prevented from starting a bus
transaction. The 750GX will still assume address-bus ownership on the cycle
BG is negated if BG was asserted in the previous cycle with other bus grant
qualifications.
State Asserted Indicates that the 750GX is the current address-bus owner. The 750GX will
not assume address-bus ownership if the bus request is internally cancelled
by the cycle a qualified BG would have been recognized.
Negated Indicates that the 750GX is not the current address-bus owner.
Timing Assertion Occurs the cycle after a qualified BG is accepted by the 750GX, and remains
asserted for the duration of the address tenure.
Negation Negates for a fraction of a bus cycle (one-half minimum, depends on clock
mode) starting the cycle following the assertion of AACK. Then releases to
the high impedance state.