Grass Valley 8912RDA - Manual (Page 17)

8912RDA/RDA-D Instruction Manual 17
Functional Description
differential line receiver in U6 or U7. Input for the channel is a balanced or
unbalanced input and therefore has selectable termination with option of
high input impedance.
U6 and U7 re-clock the data for its AES data stream. The control registers
of U6 and U7 are set to allow the entire AES3 signal with the channel status
bits to pass.
Outputs
After it is reclocked, the serial data is routed to the quad EIA-485 line
drivers (U9 and U10). Each line driver drives four balanced output lines,
which gives a fan-out of four per input.
The outputs feed a RC network that serves three purposes. The network
AC couples the signal, while creating an output resistance of 110 ohms to
match the cable impedance, limits the rise and fall times to meet the AES
specification and in conjunction with a ferrite bead, reduces EMI. Output
data comes directly from U6 and U7.
Controller
The controller is an OTP (one time programmable) P87LPC764. On power
up, the microcontroller configures U6 and U7 and reads an internal register
in U6 and U7 to determine if U6 or U7 is locked or not to the incoming AES
input. The controller provides communications between a host processor
and the 8912RDA-D.
Lock LED
The microcontroller drives the Lock LEDs, DS1 and DS2. If either LED is
on, it indicates that U6 or U7 were able to lock onto the incoming AES
signal.
Linear Regulator
The voltage regulators are monolithic integrated circuits with a fixed
voltage output of +5 volts. The regulators employ internal current limiting
and thermal shutdown. There are two +5V regulators, one for the input and
reclocking chip and another for the output drivers.