Ensemble Designs 4500 ASI and SMPTE 310M Converter and MPEG Transport Processor - Manual (Page 6)

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Model 4500 MPEG Stream Processor
Transport Stream Bit Clocks and ATSC Transmissions
Having clean, accurate, low-jitter clocks in the MPEG transport stream feeding an ATSC transmitting
system is important. The 4500 offers a method to improve clock quality, thereby improving the overall
performance of the transmission system.
Importance of clock quality for broadcasting
As it affects SDI signals
An SDI signal is a bitstream that contains both information (data) and the pacing (clock) needed to
read it. In order to recover error-free data at the end of a cable, the clocking that is used to construct
the bitstream must be stable and consistent. The eye pattern display on a digital waveform monitor
can be used to verify how well a particular signal source achieves that goal. The better the clock that
underlies the data, the longer a piece of cable that an SDI signal can transit without error.
When a serial clock’s frequency is unwavering and free of phase shifts and noise that would cause the
clock edges to jitter, the data can be easily recovered because the difference between the symbols (the
ones and zeros in the bitstream) is clear and unambiguous.
As it affects ATSC digital transmission
There are two critical differences between ATSC and SDI expressed in terms of restrictions in ATSC’s
8 VSB modulation.
The first difference is that the channel bandwidth of ATSC is severely restricted compared to an
SDI signal traveling on a piece of coaxial cable. The effective bandwidth of that cable is several
times greater than the fundamental bit rate being transmitted. The consequence of the bandwidth
restriction is that the 8 VSB eye is much smaller than the SDI eye.
The second difference is ATSC’s use of eight symbols (discrete amplitude levels or voltage levels)
versus two for SDI. At each sampling point (clock) in the ATSC signal, the signal can take on any one of
eight different voltage levels (symbols). The digital waveform monitor displays this as a stack of seven
eyes, created by the eight discrete voltage levels possible at the sampling point.
The MPEG encoder generates the digital clock seen in the 8 VSB eye pattern. The frequency accuracy,
purity, and stability of the computer grade clocks is sufficient for sending data from point to point on
a coaxial cable. However, these computer grade clocks are not sufficient for creating a waveform as
complex as 8 VSB modulation.
Placing an Avenue 4500 MPEG Stream Processor in front of the ATSC Exciter helps the transmitter
present the cleanest possible digital signal.