Sundance SMT365 - Manual (Page 12)

Version 2.3 Page 12 of 28 SMT365 User Manual
FLASH
An 8MB Flash ROM is connected to the DSP in the EMIFB CE1 & CE2 memory
spaces. The ROM holds boot code for the DSP, configuration data for the FPGA, and
optional user-defined code.
The flash is 16-bit wide. The boot code is stored in 8-bit mode as this is the way the
DSP boots. The FPGA data and user application are stored in 16-bit.
The EMIFB CE1 and CE2 space control registers should be programmed with the
value 0xFFFFFF03 to access the flash in 8-bit mode and 0xFFFFFF13 in 16-bit
mode.
As the DSP only provides 20 address lines on its EMIFB, both CE1 & CE2 are used
to access this device. This in itself allows the direct access of 4MB. A paging
mechanism is used to select which half of the 8MB device is visible in this 4MB
window.
As the EMIFB CE1 & CE2 memory spaces alias throughout the available range, the
flash device can be accessed using the address range 0x67E00000-0x681FFFFF.
This gives a 4MB continuous memory space.
The flash can be divided into the four logical sections shown in the following figure
(paging bit is bit 21).
Page0
(2 MBytes)
Page1
(2 MBytes)
Page1
(2 MBytes)
0x67C00000
0x67E00000
0x68000000
0x68200000
0x68400000
CE1
CE2
Page0
(2 MBytes)
Section 1
Section 2
Section 3
Section 4
Figure 1: Flash logical sections
To change the state of the page bit, you need to write to the following address as
shown (the data written is irrelevant):
Address Flash page selected
0x6C000000 Page 0 (1
st
and 3
rd
sections enabled)
0x6C000001 Page 1 (2
nd
and 4
th
sections enabled)
The EMIFB CE3 space control register should be programmed with the value
0x00CFFF03 for optimum access speed to the CPLD.