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Global bus – Sundance SMT335 User Manual

Page 15

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Version 3.0

Page 15 of 34

SMT335 User Manual

Module SDBCLK

Clock

Speed

0 50MHz

SMT335

1 100MHz

0 41MHz

SMT375

1 83MHz

Global bus

The SMT335 provides one global bus interface.

See general firmware description

The latest global bus interface is double buffered for dma so that it can read ahead
the next buffer while the first one is being read by the DSP. Similarly a buffer is being
written while the previous one is being sent.

The important thing is to set the global bus operation register before enabling the
global bus interrupt on an external interrupt line so that the interrupt generated is the
one relevant to the operation (read/write).

This has changed for the SMT335 firmware as it used to need the dma event to be
forced for a write and that the external interrupt was enabled before the operation
register was set. This is the only change needed when updating from a version of the
SMT335 prior to 3.13.6.

Note for SMT310, SMT310Q, SMT300, SMT300Q

Burst Transfer across a 1KBytes page boundary is only supported from version
3.13.6 of the firmware.

To transfer over the PCI the global bus is set-up to be able to perform burst transfer
across the PCI bridge chip. A burst transfer is happening whenever the global bus
transfer size register is set to transfer more than one word at a time. During a burst a
word is transferred on every clock cycle.

The PC memory can be accessed through aperture 0 of the PCI Bridge but a burst
transfer must not cross a 1KBytes boundary (256 words). This is because the page
size of the bridge chip is 1KBytes.

In other words burst transfer must always be ended on a page boundary. For
example you should never burst from the pci address XXXXX3FCH to XXXXX400H.
Address XXXXX400H would actually be targeting address XXXXX000H in the pci
address space as the page accessed by this burst was in the address range
XXXXX000H - XXXXX3FCH.

To make sure a page crossing does not happen during burst access an address
alignment has to be performed. The global bus transfer size has to be reduced not to

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