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Emif control registers – Sundance SMT335 User Manual

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Version 3.0

Page 12 of 34

SMT335 User Manual

EMIF Control Registers

The C6000 contains several registers that control the external memory interface
(EMIF). There is one global control register and a separate register for each of the
memory spaces CE0 to CE3. A full description of these registers can be found in the
C60000 Peripherals Reference GuideError! Reference source not found.Error!
Reference source not found.
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.

The standard bootstrap will initialise these registers to the following values:

GC (global control)

0x00003779

0x0000377D

For half speed SBSRAM
For full speed SBSRAM (default)

CE0 0x00000040

Indicates

SBSRAM

CE1

0x30FF3F03

Defines asynchronous memory timings

CE2 0x00000030

Indicates

SDRAM

CE3

0x00000030

VIRTEX FPGA

Note: Bits 12&13 of the Global control register are listed as 'reserved' in the current
TI documentation. With earlier versions of the C6000 silicon, these 2 bits controlled
the polarity of two clock outputs from the device. To maintain code compatibility for all
of our version modules, we have left our documentation with bits 12&13 set.

SBSRAM

Memory space CE0 is used to access 512KB of zero wait-state SBSRAM over the
C6000 external memory interface (EMI).

SBSRAM is normally set to run at the speed of the C6000 core clock, but the GC
register can be used to reduce this to one half of the core clock speed. The
appropriate setting has to be determined in conjunction with the C6000 core speed
and the external memory speed; refer to Clock Speed on page Error! Bookmark
not defined.
for further details.

SDRAM

Memory space CE2 is used to access 16MB of SDRAM over the EMI. The SDRAM
operates at one half of the core clock speed.

FLASH

A 512KB Flash ROM device is connected to the C6000 EMI. This device is
accessed, a byte at a time, with word addresses from 0x0140 0000 to 0x015F FFFF
using strobe CE1 in 32-bit asynchronous mode. Each 32-bit load will give 8 bits of
data in bits 7–0 of the result; the state of bits 31–8 is undefined.

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