Sundance FC203A User Manual
Page 10
Page 10 of 10
Revision 0.5
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email:
www.sundancedsp.com
5. VERIFICATION
The firmware module will be supported by two types of test benches. In all cases, compilation is
performed using
gmake
(distributed with CCS3.0 or greater)
2
.
Unit Test Benches
A C- Reference Model is implemented as a Diamond/DSP Task. This model is not yet
implemented as of this revision.
Resource and Performance Analysis Benches
A mechanism to obtain the resource utilization of the FC203A core is provided. The basic
principle is to generate a “baseline” implementation of the target FPGA that contains a ‘stub’.
The ‘stub’ has all the same inputs and outputs, but is a trivial implementation of the FPGA task.
This “baseline” is compared to a real instantiation of the FC203A module. The stub FPGA task
is provided as ‘
FC203A\FC203A_base.fcd
’.
Comparing the two MAP report files and subtracting the Slices, BRAM and MPY in use
provides an accurate real-word estimate of the resources used by the FC203A module.
Finally, Diamond application configuration files are provided which enable the FC203A module
to be instantiated into a supported single (stand-alone) FPGA board. By connecting the dataflow
inputs of the FC203A to SDB resources, and the CTRL_IN to the default Comport (CP3,
typically) resource, a hardware reference is created which can be added to any system and
operated at line rate.
The configuration files and makefile for accomplishing these are provided in the
analysis\
folder.
MODULE
FPGA
Slices
BRAM
MPY
F
MAX
(MHz) Notes
SMT348-10 XC4VSX55-10
110
0
0
262
SMT365-8-1 XC2V1000-4
108
0
0
172
SMT368-10 XC4VSX35-10
110
0
0
262
SMT368-12 XC4VSX35-12
110
0
0
331
SMT398-8000 XC2V8000-4
108
0
0
172
SMT398-VP70 XC2VP70-6
100
0
0
227
SMT417 XC2VP50-5 99
0
0
202
Table 4 –FC203A Performance Estimates and Resource Utilization
The results in table 4 are estimates only, based on very lightly-loaded FPGA configurations.
Some trade-off between slice usage and speed is possible depending on synthesis and fitting
options. Exceeding F
MAX
may cause logic errors and unexpected results, which can be
exceedingly hard to debug. It is the system designer’s responsibility to avoid this condition.
2
Only gmake has the necessary syntax to effectively implement the build system. Contact Sundance DSP for
assistance if your installation lacks CCS.