Sundance SMT784 v.1.0 - Manual (Page 20)

Version 1.0 Page 20 of 31 SMT784 User Manual
The firmware inside the FPGA implements the communication interfaces required to
allow the data transfer between the SMT784 and the Host PCI/PCIe.
The host transfers data with the SMT784 using the X-Link. There is one X-Link
instantiated per communication resource (Flash, SMT384, DDR, RSL). All the X-Link
interfaces are connected to the PCI core and can be accessed from the Host. The
default firmware currently provides two communication resources: one Comport for
interfacing the CPLD and Flash to the Host and one RSL currently used for ADC
register control and data acquisition. Refer to the SMT6400 and SMT6500 for more
information concerning the communication resources.
A Xilinx PCI IP core is used to allow data transfer between the Host machine and the
X-Link.
Xilinx PCI Core
The PCI core supports target accesses and initiator accesses. Data transfers are
implemented using initiator accesses to ensure maximum bandwidth. For this
purpose a DMA engine is connected to the X-Link and the PCI core to transfer the
data.
The PCI/PXIe interface used in this design was generated by using the Xilinx Core
Generator (core version 4.8) included with ISE 10.1 Foundation software. The user is
free to implement the included netlist into custom firmware, but if there is a need to
re-generate the IP core, the full license must be purchased from Xilinx.
Licensing information and how to purchase this core can be found at the Xilinx
website:
www.xilinx.com
Driver
The SMT784 is supported by the SMT6300 that provides the Windows driver for the
board.
Registers
All the addressable resources are located in the BAR1.
The communication resources are presented to the host machine as X-Link
interfaces. The addresses of the X-Link and the number of X-Link are available from
the X-Link table of content found in the firmware.
Refer to the X-Link documentation for a description of the registers in the X-Link.
The other registers available in the firmware are the following:
Reset register (BAR1 – 0x00000000)
Writing ‘1’ to the reset register will cause the SMT145 and the TIM plugged on it to be
reset. The reset is de-asserted automatically after a few milliseconds.